A conventional multilayer semiconductor device uses Bus-Line system of arrangement, in which a device region and a signal line region are arranged separately. In response to improvement of integration of ICs, another type of conventional multilayer semiconductor device including a device block located under a signal line region has been proposed.
A Japanese Patent Publication, Kokai Heisei 2-284229, describes a bus-line type of semiconductor memory in which same phase of signal lines are arranged together to be a bunch so that next two signal lines in a bunch are arranged with a small space from each other but next two bunches are arranged with a large space from each other. This kind of arrangement can prevent a semiconductor circuit, to be mounted in the device, from misoperating.